The cad/yosys port

yosys-0.69 – Yosys Open SYnthesis Suite

Description

This is a framework for RTL synthesis tools. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains.

Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the yosys C++ code base.
WWW: https://github.com/YosysHQ
Only for arches
aarch64 aarch64 alpha amd64 amd64 arm arm hppa i386 i386 mips64 mips64 mips64el mips64el powerpc powerpc powerpc64 powerpc64 riscv64 riscv64 sparc64 sparc64
Categories:
cad lang/python

Library dependencies

Build dependencies

Run dependencies